100Gb/s OTN G.709 FEC Core
The XCO4GFEC core consists of independent XCO4GFECE encoder and XCO4GFECD decoder cores. Thefunctional block diagrams provided below show the core with basic control inputs and count outputs. TheXCO4GFEC core was designed hierarchically in order to provide flexibility to the system designer.
The encoder can be instantiated at the xco4gfece_core level of the design if the designer wishes to instantiate theraw encoder engine with no error insertion capability and no register interface.Alternately, it can be instantiated atthe xco4gfece level to include the single bit error insertion capability, or the xco4gefece_r level to also include the register interface.
The decoder can be instantiated at the xco4gfecd_core level of the design if the designer wishes to instantiate theraw decoder engine with no internal RAMS. This level is appropriate if the designer wishes to share the decoderRAMS with another FEC design. Alternately, the decoder can be instantiated at the xco4gfecd level to include theRAM instantiations and the BER alarm. The xco4gfecd_lc level of the design includes latch & clear accumulatorsfor corrected one, corrected zeroes, corrected symbols, and uncorrectable codewords. If a full register interface isdesired, the xco4gfecd_r level can be instantiated. In this case all of the control registers and performance monitorswill be accessible via a 16-bit register interface.
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