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Single Port, Ultra Low Power, Low Voltage, GF 22FDX, Single Port Compiler
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100Gb/s OTN G.709 FEC Core
The Xelic 100G OTU4 GFEC (XCO4GFEC) core performs FEC encoding and decoding of OTU4 frames using 16byte-interleaved RS(255,239) codewords as specified in ITU-T G.709 Interfaces for the optical transport network(OTN). The XCO4GFEC contains independent encoder and decoder functions fully compliant with the G.709specification and has been through extensive interoperability testing. Corrected errors and uncorrectable codeworddetection is provided on an OTL4.10 logical lane basis along with a configurable High BER alarm. Line and systemside data is transferred at an OTU4 rate using a 640-bit data bus operating at a nominal frequency of 174.7MHz.
The XCO4GFEC core consists of independent XCO4GFECE encoder and XCO4GFECD decoder cores. Thefunctional block diagrams provided below show the core with basic control inputs and count outputs. TheXCO4GFEC core was designed hierarchically in order to provide flexibility to the system designer.
The encoder can be instantiated at the xco4gfece_core level of the design if the designer wishes to instantiate theraw encoder engine with no error insertion capability and no register interface.Alternately, it can be instantiated atthe xco4gfece level to include the single bit error insertion capability, or the xco4gefece_r level to also include the register interface.
The decoder can be instantiated at the xco4gfecd_core level of the design if the designer wishes to instantiate theraw decoder engine with no internal RAMS. This level is appropriate if the designer wishes to share the decoderRAMS with another FEC design. Alternately, the decoder can be instantiated at the xco4gfecd level to include theRAM instantiations and the BER alarm. The xco4gfecd_lc level of the design includes latch & clear accumulatorsfor corrected one, corrected zeroes, corrected symbols, and uncorrectable codewords. If a full register interface isdesired, the xco4gfecd_r level can be instantiated. In this case all of the control registers and performance monitorswill be accessible via a 16-bit register interface.
The XCO4GFEC core consists of independent XCO4GFECE encoder and XCO4GFECD decoder cores. Thefunctional block diagrams provided below show the core with basic control inputs and count outputs. TheXCO4GFEC core was designed hierarchically in order to provide flexibility to the system designer.
The encoder can be instantiated at the xco4gfece_core level of the design if the designer wishes to instantiate theraw encoder engine with no error insertion capability and no register interface.Alternately, it can be instantiated atthe xco4gfece level to include the single bit error insertion capability, or the xco4gefece_r level to also include the register interface.
The decoder can be instantiated at the xco4gfecd_core level of the design if the designer wishes to instantiate theraw decoder engine with no internal RAMS. This level is appropriate if the designer wishes to share the decoderRAMS with another FEC design. Alternately, the decoder can be instantiated at the xco4gfecd level to include theRAM instantiations and the BER alarm. The xco4gfecd_lc level of the design includes latch & clear accumulatorsfor corrected one, corrected zeroes, corrected symbols, and uncorrectable codewords. If a full register interface isdesired, the xco4gfecd_r level can be instantiated. In this case all of the control registers and performance monitorswill be accessible via a 16-bit register interface.
Features
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO4GFEC core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.709 specification.
- Encoder includes single bit error insertion for diagnostic purposes.
- Provides outputs for scrambled line values of corrected ones and corrected zeroes by OTL4.10 Logical Lane
- Provides corrected symbols, corrected codeword, and uncorrected codeword outputs.
- Architecture facilitates RAM sharing with other EFEC cores.
- Provides a configurable High BER alarm.
- Overall latency of less than 0.90 us.
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