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100Gb/s OTN Staircase Enhanced FEC Core
GENERAL DESCRIPTION
The XCO4EFECSC is a high-gain FEC core, which is compliant with the Staircase FEC code, proposed by Cortina. The term staircase is used because the contents of the OTU frames are re-arranged into steps of a staircase, such that every row and every column in the staircase is a valid codeword. This structure of this code also ensures that each bit is involved in two orthogonal codewords.
The codewords are made up of a triple-error-correction BCH code, BCH(1022, 990, 3) defined by p(x)x10+x3+1, m10. This code has a codeword length of 1022, payload length of 990 and can correct up to 3 bit errors. Its generator polynomial, g(x) (x10+x3+1) (x10+x3+x2+x+1) (x10+x8+x3+x2+1) (x2+1)
The XCO4EFECSC is a high-gain FEC core, which is compliant with the Staircase FEC code, proposed by Cortina. The term staircase is used because the contents of the OTU frames are re-arranged into steps of a staircase, such that every row and every column in the staircase is a valid codeword. This structure of this code also ensures that each bit is involved in two orthogonal codewords.
The codewords are made up of a triple-error-correction BCH code, BCH(1022, 990, 3) defined by p(x)x10+x3+1, m10. This code has a codeword length of 1022, payload length of 990 and can correct up to 3 bit errors. Its generator polynomial, g(x) (x10+x3+1) (x10+x3+x2+x+1) (x10+x8+x3+x2+1) (x2+1)
Features
- Suitable for FPGA and/or ASIC implementations.
- Compatible with Cortinas staircase high gain FEC.
- Decoder includes multiple iterative stages of BCH error correction
- Provides corrected bit outputs.
- Provides corrected codeword outputs
- Provides uncorrected codeword outputs for the last iteration
- Architecture facilitates RAM sharing with other EFEC cores.
- Overall latency of 2.25Mb.
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