The 100GBase-CR4 / 100GBase-KR4 PCS Core is compliant with the IEEE802.3bj latest Draft 1.4 specification and is optimized for ASIC technologies.
The 100GBase-CR4 / 100GBase-KR4 PCS Core implements the mandatory Reed Solomon Forward Error Correction (RS FEC) encoding and error detection blocks and, optionally, the RS FEC error correction block. When implemented, the error correction block can be bypassed with software programming to reduce the application latency.
The 100GBase-CR4 / 100GBase-KR4 PCS Core combines, in a single Intellectual Property (IP) Core, the RS FEC Block with proven 100Geth MLD, PCS, Autonegotiation and link Training functions.
The PCS is programmable with a simple parallel register interface or a serial Extended MDIO slave. The PCS also implements the mandatory link status and error detection for efficient silicon and application bring up.
The PCS can be connected, with no Glue Logic, to industry standard Serdes with a 40-Bit or a 64-Bit interface and, to design efficient and compact 100Geth backplane controllers, to silicon proven 100Geth MAC Core.
The RS FEC Block is also available integrated in MorethanIP silicon proven multi-rate, multi-channel 1/10/40/100Geth Hydra-4 MAC / PCS Core which provides a universal programmable Ethernet interface solution that meets legacy, current and future applications requirements.
The 100GBase-KR4/CR4 and Hydra-4 IP Cores are delivered with the MorethanIP user-friendly configuration graphical user interface, through which designers can easily eliminate features that are not required, reducing unit costs and simplifying integration.