10G Managed Ethernet Switch (MES) IP core features a full-speed, Head-Of-Line effect free crossbar matrix that allows continuous transfers between all the ports. It supports up-to 32 ports with different line speed. The switch implements a Store & Forward switching approach to fulfill Ethernet standard policy regarding frame integrity checking.
The internal micro-architecture includes disruptive enhancements in order to ensure a reliable operation of the switch even in critical use-cases. As an example, Virtual Output Queues combined mirrored MAC tables allow simultaneous access to the matrix at maximum data throughput. The IP does not request any external memory.
10G MES is a multi-speed (100M/1G/2.5G/5G/10G s) switch IP and supports IEEE 1588 V2 Transparent Clock functionalities. This features modifies PTP event messages taking into account the time spent crossing the switch. This scheme improves distribution accuracy by compensating delivery variability across the network. Specifically, 10G MES also supports IEEE 1588 V2 One Step Transparent Clock Peer-to-Peer (P2P) functionality by using independent hardware for each port. This feature allows compensating the residence time but also the delay of each link.
The IP includes MII/GMII/RGMII native interfaces for Ethernet PHY devices and it can be combined with Xilinx IP to support RMII/SGMIIQ/SGMII and USXGMII among other interfaces. It also provides an AXI4-Stream interface to easy the connection to other IPs Cores like SAScrypt for wire-speed security.