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100MHz Differential PGA Programmable gain amplifier
The S3RXPGAT28HPCP is a Programmable Gain Amplifier with -17 to 27dB gain. The gain is programmable with 1dB steps with fast gain settling. Block provides trimmable 100 Ohm input termination and bandwidth of 100MHz.
The S3RXPGAT28HPCP has been implemented in TSMC 28nm HPC+ option with 0.9V control signal domain. However, it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
A range of supporting and compatible blocks such as Analog-to-digital Converters (ADC), Low Drop-out regulators (LDO), bias and reference blocks, etc. are also available.
The S3RXPGAT28HPCP has been implemented in TSMC 28nm HPC+ option with 0.9V control signal domain. However, it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
A range of supporting and compatible blocks such as Analog-to-digital Converters (ADC), Low Drop-out regulators (LDO), bias and reference blocks, etc. are also available.
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Block Diagram of the 100MHz Differential PGA Programmable gain amplifier
100MHz Differential PGA IP
- 210MHz Differential PGA
- Line Driver Differential Current Amplifier IAMP 100MHz
- 100MHz single-ended to differential clock buffer for UMC 40nm LP.
- 100MHz Reference Clock Single-end to Differential Buffer for PCIE Gen.I; UMC 0.13um HS/FSG LOGIC/MIXEDMODE Enhance Process
- Current Input Analogue Front End with Programmable Gain Amplifier (PGA) and Fully Differential Voltage Output, TSMC 180nm
- IGAADCR13A, TSMC CLN55LP 12Bit 100MHz Pipelined ADC [1ch]