The S3RXPGAT28HPCP is a Programmable Gain Amplifier with -17 to 27dB gain. The gain is programmable with 1dB steps with fast gain settling. Block provides trimmable 100 Ohm input termination and bandwidth of 100MHz.
The S3RXPGAT28HPCP has been implemented in TSMC 28nm HPC+ option with 0.9V control signal domain. However, it is readily portable to any similar manufacturing process. Any activity of this nature can be fully supported.
A range of supporting and compatible blocks such as Analog-to-digital Converters (ADC), Low Drop-out regulators (LDO), bias and reference blocks, etc. are also available.
- 28nm TSMC HPC+ Process
- 2.5V supply, 0.9V control interface
- Differential input/output amplifier
- Deep N-well for noise isolation
- On-chip 100 Ohm input termination
- Programmable standby termination resistor
- Programmable gain/attenuation -17 to 27dB
- Up to 4dBm input power
- 50dB MTPR with PAPR 16dB
- 100MHz Bandwidth
- Low power mode with 50MHz Bandwidth
- Compact die area
- Low Active power consumption
- Low power mode.
- Standby mode
- DC offset calibration
- This IP and its component sub-blocks, may be tailored for specific system implementation requirements as part of a design services engagement and/or may be optimally integrated with a broad portfolio of AFE Building Block IP.
- The PGA can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- PLC, G.hn, G.Fast Communications
- Multi-mode and multi-band wireless/wireline systems
- Customizable for various wireless/wireline applications
Block Diagram of the 100MHz Differential PGA Programmable gain amplifier