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1024 State 3GPP2 Viterbi Decoder
The 3GPP2 Viterbi Decoder is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed to decode 3GPP2 Reverse Traffic Channel encoded data as well as other custom coding solutions.
Features
- 1024 state (constraint length 11) 3GPP2 compatible Viterbi decoder
- Up to 258 MHz internal clock
- Up to 14.4 Mbit/s
- Rate 2/3, 1/2, 1/3 or 1/4
- Optional or standard code polynomials
- 8–bit signed magnitude or two's complement input data
- Optional continuous, terminated (1 to 246 data bits) or tail-biting (32 to 256 data bits) decoding
- Estimated channel bit error outputs
- Optional serial (continuous only) or parallel data input
- Optional automatic synchronisation for rate 1/2 QPSK and rate 1/2 to 1/4 BPSK
- LUTs: Virtex–4 8342, Virtex–5 7292, Virtex–6 7294, Spartan–6 7287, Artix–7 7306, Kintex–7 7605. 16 16Kb BlockRAMs.
- Asynchronous logic free design
- Free simulation software
- Available as EDIF core and VHDL simulation core for Xilinx Virtex-II, Spartan-3, Virtex-4, Virtex-5, Virtex-6, Spartan-6 and 7 Series FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
- Available as VHDL core for ASICs
Deliverables
- All Licenses
- EDIF Core
- VHDL Simulation Core
- Test vector generator
- ASIC License
- VHDL ASIC Core
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