Comcores 10G/25G Ethernet MAC provides a complete IEEE 802.3 Ethernet Layer 2 solution. The MAC IP core performs the Link function of the 10G/25G Ethernet Standard and is a low latency cut-through implementation reaching best in market results while still keeping size at a minimum. The core is fully configurable and is prepared for IEEE1588 integration and easy interfacing with Comcores 10G/25G PCS solution.
The Ethernet MAC Core, on the Client side, implements a 64-bit AXI-S interface for Express and Preemptable traffic respectively while having a standard XGMII interface on the PHY side.
- Delivering Performance
- Designed to IEEE 802.3-2012 specification
- Ultra low latency and compact implementation
- Full duplex Ethernet interfaces
- PCS sublayer for 10/25 Gb/s operation available as separate block
- Richly Featured
- Deficit Idle Count for maximum data throughput supported
- FCS generation supported
- Comprehensive statistics gathering
- Independent TX and RX Maximum Transmission Unit (MTU) frame length
- Very easy integration with standard Xilinx AXI4 Lite control interface or APB
- Highly Configurable
- 10G/25G data rates with cut-through supported
- Ready for IEEE 1588 integration
- Comes with XGMII and AXI-S interface
- Silicon Agnostic
- Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.
- The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.
Block Diagram of the 10G/25G Ethernet MAC IP Core