10G Ethernet Switch

Features

• Delivers Performance:
• Automatic MAC addresses learning and aging
• Programmable FW operation with Static or Dynamic switching table entries
• Full duplex Ethernet interfaces
• Optimized for size
• Easy to use
• XGMII interfaces for attaching external Physical Layer devices (PHY)
• Very easy integration with standard Xilinx AXI4 Lite control interface
• Can be used in managed or unmanaged implementations
• Highly Configurable
• Up to 20 ports configurable at compile time
• Configurable queuing behavior (round-robin, fair queuing, etc.)
• Support Ethernet Multicast, Broadcast with flooding control to avoid unnecessary duplication of frames
• Configurable support for 1588 PTP Transparent Clock functionality
• Silicon Agnostic
• Designed in VHDL-93 and targeting any RTL implementation like ASICs, ASSPs and FPGAs.

Benefits

• Architecture supports a large number of ports
• Large number of features supported default
• Ultra-compact size
• Silicon Agnostic
• Customization can be provided

Deliverables

• The IP core comes deeply verified and with an extensive documentation that, among others, includes Product Brief and User Manual. The core will by default come in an encrypted format. Source code option is available.

Block Diagram of the 10G Ethernet Switch IP Core

• see the entire 10G Ethernet Switch datasheet
• get in contact with 10G Ethernet Switch Supplier