10G Fibre Channel FC-1 Core
Features
- Optional Media independent XGMII (DDR) or 64-Bit (SDR) Interface to 10G FC-2
- Line Scrambler and Descrambler
- 64B/66B Encoder and Decoder
- Elastic Buffers for clock domain transfer to/from XGMII interface
- Optional Management Data Interface (MDIO)
- Test Pattern Generator/Checker for link testing purposes. Implements Square Wave and Pseudo Random Tests
- Core Flexibility offering stand-alone or combined modular system for single-chip solutions
- Technology Support for CPLD, FPGA and ASIC
- Design Kit comes with extensive checking models enabling fully automated design verification and testing for standard compliance and error behavior, enabling for fast turn-around design cycles
- Available as CPLD/FPGA binary or VHDL or Verilog RTL source code including all necessary simulation and synthesis scripts and testbenches
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