The 10G-KR Multi-Protocol PHY IP from Cadence Design Systems is a hard PHY macro for the TSMC 28HPM process. It supports 10G-KR (IEEE802.3) PCIe 3.0, Xaui, QSGMII and SGMII specifications at speeds up to 10GT/s. The Cadence 10G-KR Multi-Protocol PHY IP is designed to easily integrate with a Cadence IP Factory PCIe & Ethernet controllers, or any third party controller with standard interface and delivers high eye-margin at low power for 10G operation. Numerous auto-calibrated circuits and programmable state machines are implemented for PHY performance tuning and improved yield. Cadence patented SurePHYr LC tank PLL provide a low power optimized jitter performance design. Extensive BIST and Observe features are implemented for on-die/packaged part testing and bring-up. The 10G-KR Multi-Protocol PHY IP from Cadence Design Systems can be used to support a wide range of applications including: Low Power Storage Applications,High-performance Storage,Supercomputing, Networking Applications.