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10G-KR Multi-Protocol PHY (+PCIe3) - FlipChip - TSMC 28HPM
The 10G-KR Multi-Protocol PHY IP is a hard PHY macro for the TSMC 28HPM process. It supports 10G-KR (IEEE802.3) PCIe 3.0, Xaui, QSGMII and SGMII specifications at speeds up to 10GT/s. The 10G-KR Multi-Protocol PHY IP is designed to easily integrate with any controller with standard interface and delivers high eye-margin at low power for 10G operation. Numerous auto-calibrated circuits and programmable state machines are implemented for PHY performance tuning and improved yield. The patented SurePHYr LC tank PLL provide a low power optimized jitter performance design. Extensive BIST and Observe features are implemented for on-die/packaged part testing and bring-up.
The 10G-KR Multi-Protocol PHY IP can be used to support a wide range of applications including: Low Power Storage Applications,High-performance Storage,Supercomputing, Networking Applications.
The 10G-KR Multi-Protocol PHY IP can be used to support a wide range of applications including: Low Power Storage Applications,High-performance Storage,Supercomputing, Networking Applications.
Features
- Compatible with IEEE Standard 802.3, and PCIe 3.0, 2.0 , 1.1 specifications
- Supports XAUI, SGMII, and QSGMII applications
- LC Tank VCO/PLL for improved performance
- Automatic calibration of analog circuits and offset correction for minimum BER
- 5-tap adaptive decision feedback equalization for long-reach support
- Bifurcation and inverse bifurcation support
- Fully adaptive, continuous-time, linear equalizer
- PCS supports the PIPE 4.0 specification
- Programmable 3-tap transmitter finite-impulse
- response filter with polarity inversion
- Supports x1, x2, x4, x8, and x16 configurations for PCIe and 4x10G, 10x10G, and 1G for Ethernet
Deliverables
- Standards integration views: timing, physical views, LEF, DRC, LVS, ANT
- GDSII layout
- Complete documentation customized to your specific configuration
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