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10G-KR PHY - FlipChip - TSMC 16FF
The Cadence 10G-KR PHY IP is a hard PHY macro consisting of a Physical Media Attachment (PMA) layer and a soft Physical Coding Sublayer. It is optimized for 10G Ethernet, and provides high performance at low power and low area. Compliant with IEEE Standard 802.3 10GBASE-KR requirements (Clause 51), the Cadence 10G-KR PHY IP is highly-configurable allowing the PHY to be customized to your specific needs.
Numerous auto-calibrated circuits, programmable state machines throughout the design for PHY performance tuning, and the dual LC tank PLL provide a low-power optimum performance design. All standard power states, including VAUX, are supported.
Numerous auto-calibrated circuits, programmable state machines throughout the design for PHY performance tuning, and the dual LC tank PLL provide a low-power optimum performance design. All standard power states, including VAUX, are supported.
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