The Algo-Logic Systems' TCP Endpoint implements a full, reliable streaming network stack in FPGA logic. It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces. It allows applications in logic to be directly connected to Internet Protocol (IP) interfaces. This soft core allows opening, maintaining, and closing TCP Connections via Ethernet to other hardware or software endpoints.
The mature, reliable, and network-tested TCP Endpoint delivers high performance with ultra-low latency. It runs at the full 10 Gigabit Ethernet line rate with a clock speed synchronous with a MAC and application processing logic. It supports full duplex rates of 20 Gbps per instance. The implementation is portable between Altera and Xilinx FPGA devices and has been deployed multiple platforms.
Algo-Logic’s TCP Endpoint is available as a pre-integrated component in low latency applications. It has been deployed in customer applications including pre-trade risk-checks, complete tick-to-trade applications, and other flow processing applications. Algo-Logic provides in-house engineering support to ensure complete solution delivery with support for end-system and application-level fastest deployments.
- FullTCP/IP stackin FPGA logic
- Layer 1: IEEE802.3
- Layer 2: IEEE802.3, ARP
- Layer 3: IPv4 and ICMP
- Layer 4: TCP
- Ultra-low latency
- RTL design for optional performance
- Optional cut-through for receive (RX) and transmit (TX) data.
- Retransmission timeouts
- Size of shared on-chip retransmission buffer
- Option for fast retransmission
- Limits on retransmissions
- Streaming Interfaces with in-order data
- High network bandwidth
- Multiple instances allow for more than 200 Gbps to a single FPGA device Control registers
- Configurable over network or PCIe
- Supports jumbo frames
- TCP option support: MSS, window scaling, timestamps.
- Robust flow control and error control.
- Statistics for monitoring TCP sessions.
- Exchange-certified in trading systems
Block Diagram of the 10G TCP Endpoint IP Core