The core Implements a UDP/IP hardware protocol stack that enables wire-speed
communication over a LAN or a point-to-point connection. It is ideal for offloading
the host processor from the demanding task of UDP/IP and can be used in both
FPGA and ASIC designs.
The core implements ARP request, reply as well as ICMP ping reply while managing 32-entry ARP cache. The core provides the DHCP client module, which can be configured to request and acquire an IP address from external DHCP servers. The 10G UDPIP Core also supports V3 IGMP membership JOIN, LEAVE messaging. VLAN on RX and TX is supported.
The core connects to the 10G MAC layer via AXI4-Stream bus. The KMX 10G MAC core and KMX 10G PCS core are available to use.
The interfaces to the user logic are the Control Interface of AXI4-Lite bus; the five RX Interfaces and five TX interfaces of AXI4 buses and AXI4-Stream buses.
The core supports 32 RX channels and 32 TX channels. These 32 RX channels can be configured and associated with 5 RX ports. The 32 TX channels can be used to send UDP packets on any TX interface.
IP checksum validation, generation and UDP checksum validation, generation are supported. They can be enabled, disabled independently.
The core supports UDP jumbo packets with sizes up to 9K bytes. It implements UDP port number filters and raw data interface.
Thecore is designed to well handle exceptions of internal memory exhaustion and invalid incoming packets while it is designed to make the max use of internal memory to effectively deal with the TX and RX burst traffic.
Included in the delivery, there is a fully implemented reference design VHDL source code, which aims to help users integrate the KMX 10G UDPIP core into their system more easily and more efficiently.
Simulation test bench VHDL source code with 36 test cases is included in the delivery.