The Xelic 10Gb Media Independent Interface (XGMII) to 10GBASE-R PCS Core (XCI2PX) performs mapping of XGMII signals into 66-bit PCS blocks (and vice-versa) using a 64B/66B coding scheme. 10GBASE-R and 10GBASE-W applications are supported with 64B/66B transmission codes transferred at a 10Gb/s rate using a 64- bit data bus operating at 161.13Mb/s.
The XCI2PX Encode Processor accepts incoming XGMII based formatted data, encodes the data and continuously generates PCS blocks. Ordered sets and idle blocks can optionally be inserted. Programmable bypass and loopback modes of operation are supported. In addition, test block insertion is provided for diagnostic purposes. Optional scrambling is also available on the outgoing PCS based data.
The XCI2PX Decode Processor contains a configurable block synchronizer with options for block descrambling capability. A BER monitor provides an indication of signal integrity for incoming data blocks. XGMII based ordered sets are optionally inserted for programmable LOS and high BER error detection. When appropriate status has been achieved, the decode processor continuously accepts PCS blocks and generates XGMII based codes.
Performance counters are provided for the accumulation of Synchronization Block Error and high BER Error conditions in the XCI2PX decode processor. In addition, the encode processor contains Ordered Set and Test Block Mismatch performance counters. All counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCI2PX provides facility and terminal loopback modes of operation using Decode and Encode Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.