The Xelic 10Gb/s OTU2 GFEC (XCO2GFEC) core performs FEC encoding and decoding of OTU2 frames using 16 byte-interleaved RS(255,239) codewords as specified in ITU-T G.709 Interfaces for the optical transport network (OTN). The XCO2GFEC contains independent encoder and decoder functions fully compliant with the G.709 specification and has been through extensive interoperability testing. Corrected errors and uncorrectable codeword detection is provided along with a configurable High BER alarm. Line and system side data is transferred at an OTU2 rate using a 64-bit data bus operating at a nominal frequency of 167.7MHz.
The XCO2GFECE accepts incoming data and interleaves them into 16 RS codewords. Interleaving is performed by dividing 3824 bytes from each row of the ODUk frame structure into 16 codewords. The XCO2GFECE contains 16 independent instances of Reed Solomon (255,239) encoders to encode the sixteen byte-interleaved sub-rows of data. Each RS codeword is encoded to generate 16 parity check bytes for each RS codeword. A de-interleaving stage follows FEC encoding to organize outgoing data into the same format as the original incoming data.
The XCO2GFECD accepts incoming data and interleaves then into 16 RS codewords. Interleaving is performed by dividing 4080 bytes from each row of the ODUk frame structure into 16 codewords. The XCO2GFECD contains 16 independent instances of Reed Solomon (255,239) decoders to decode the sixteen byte-interleaved sub-rows of data. Each RS decoder can correct up to 8 symbol errors in one codeword. If more than 8 symbol errors are detected within a codeword, the codeword is marked as invalid. The XCO2GFECD can correct up to 128 erroneous symbols per row, 512 per OTU frame. An integrated FEC Signal Degrade block accumulates bit-errors over a fixed frame-based time interval and compares it to one of two configurable threshold constants. A BER output signal is provided to indicate 10-3 or 10-4 FEC bit error rate detection.
The XCO2GFEC implements a generic register interface for access and configuration of internal memory mapped locations. This interface is shared between encoder and decoder processors with addressing being mapped from independent base addresses. The implementation of a generic register interface allows for easy integration with other cores that may be contained in a customer application.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO2GFEC core available under flexible single use licensing terms with netlist or source code deliverables.
- Complies with ITU-T G.709 specification.
- Contains 7 parity overhead
- Provides outputs for scrambled line values of corrected ones and corrected zeroes
- Provides corrected symbols and uncorrected codewords outputs.
- Provides a configurable BER alarm select between 10-3 and 10-4.
- Overall latency of less than 1us.