English
You are here:
10GBASE-R PCS
The 10GBASE-R Physical Coding Sub-layer (PCSR) module provides the functionality of a physical coding sub-layer (PCS) on data being transferred between a de-muxed XGMII and 10 Gigabit SerDes supporting a 16 or 32 bit interface. The PCSR module provides IEEE 802.3 Clause 49 functionality and optional Clause 74 forward error correction (FEC).
Features
- 10 Gigabit Ethernet serial 10GBASE-R PCS as described in IEEE 802.3 Clause 49
- Connects to a 10 Gigabit Ethernet MAC (XGM) using a de-multiplexed XGMII interface
- Connects to a 10 Gigabit SerDes using a 16 (XSBI) or 32 bit interface
- 64/66B encoding and decoding with support for all reserved codes and signal ordered set for fibre channel use
- Data scrambler on transmit path and descrambler on receive path
- Clock tolerance compensation on receive path
- Option to allow recovered clock domain logic to be clocked at an integer division of the serial clock
- Loopback mode
- Optional MDIO interface
- Pseudo random test pattern generator and error checker with programmable seeds
- PRBS31 test pattern generator and error checker
- Square wave test pattern generator
- PRBS9 test pattern generator as described in IEEE 802.3 Clause 68
- Optional support for Forward Error Correction (FEC) sub-layer as described in IEEE 802.3 Clause 74
- Support for Energy Efficient Ethernet (EEE) by transporting Low Power Idle (LPI) as described in IEEE 802.3az Clause 49
Deliverables
- Synthesizable Verilog RTL
- Verilog testbench and scenarios
- Synthesis scripts
- User documentation
View 10GBASE-R PCS full description to...
- see the entire 10GBASE-R PCS datasheet
- get in contact with 10GBASE-R PCS Supplier