As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the 10GBASE-R PHY MegaCore® function intellectual property (IP) core for designers to easily build systems with a high throughput Ethernet connection using the fewest number of I/O pins. This 10GBASE-R PHY along with a 10GbE media access control (MAC) IP core enables an Altera® device to interface to a 10GbE network through a variety of external devices, including 10GbE PHY device or optical transceiver module.
You can implement the 10GBASE-R PHY in Altera devices with serial transceivers faster than 10 Gbps. The physical coding sublayer (PCS) is implemented in soft IP for Altera's Stratix® IV GT and Arria® V (GT and ST) and implemented as hard IP in Stratix V (GX, GS, and GT) and Arria V GZ FPGAs. The PHY management functions are implemented in soft IP. Figure 1 illustrates an example of 10GBASE-R PHY in Altera devices.
- SOPC Builder Ready: No
- Qsys Compliant: No