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10Gbit/s Ethernet MAC
The 10G Ethernet MAC (XGMAC) for FPGAs is an ultra-low latency, low gate count 10Gbit IP that simplifies the FPGA integration of ultra-fast 10Gbit/s Ethernet.
XGMAC is an all- RTL design to achieve the lowest possible latency, and is fully compliant with the IEEE802.3 specification. The FIFO application interface can be configured for either Xilinx or Altera.
XGMAC is easily integrated into high end FPGAs such as Virtex 6, 7 series (Xilinx) & Stratix, Arria (Altera).
The smooth integration of the XGMAC into your product is supported by reference designs, concise code documentation, and access to expert engineers.
XGMAC is an all- RTL design to achieve the lowest possible latency, and is fully compliant with the IEEE802.3 specification. The FIFO application interface can be configured for either Xilinx or Altera.
XGMAC is easily integrated into high end FPGAs such as Virtex 6, 7 series (Xilinx) & Stratix, Arria (Altera).
The smooth integration of the XGMAC into your product is supported by reference designs, concise code documentation, and access to expert engineers.
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Block Diagram of the 10Gbit/s Ethernet MAC IP Core
Ethernet IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Ethernet Switch / Router IP Core - Efficient and Massively Customizable
- 25G Multi Rate SerDes PHY - TSMC 28nm HPC+
- 32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
- Gigabit Ethernet 802.3 MAC - Media Access Controller
- TCP/IP - 10&25Gbit/s Ethernet TCP Offload Engine