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112G LR Multi-protocol SerDes PHY
An ADC-based long-reach (LR) 112G SerDes PHY solution providing leading-edge performance and power efficiency for next-generation networking and hyperscale data center applications.
The Rambus 112G LR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance across challenging long reach signaling environments for next-generation networking applications. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 10.3 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the PHY architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.
The Rambus 112G LR Multi-Protocol SerDes (MPS) PHY is a comprehensive IP solution designed to provide best-in-class performance across challenging long reach signaling environments for next-generation networking applications. The 112G MPS PHY supports PAM-4 and NRZ signaling and data rates from 10.3 to 106.25 Gbps across copper and backplane channels with more than 35dB insertion loss. At the heart of the PHY architecture is an ADC operating at 56 GS/s that allows for adjustable power and improved performance while providing low BER.
Features
- Supports up to 4 duplex lanes and data rates from 10.3 to 106 Gbps
- Embedded micro-processor enables firmware-controlled PMA configuration, initialization and adaptation for maximum flexibility and minimum ASIC integration effort
- RX front end with on-chip capacitors supports both AC-coupled and DC-coupled channels
- Configurable architecture enables power saving models for low and medium loss channels
- Programmable TX/RX equalizers including: ·· Multi-tap digital FFE and DFE for extended channel reach
- A centralized LC-PLL supports a wide range of reference clock frequencies and lane operating frequencies
- Differential reference clock inputs selectively sourced from dedicated pins or internal ASIC interface pins
- Direct register control available for all PMA functions
- Flexible layout supports placement along all ASIC edges in an ASIC
- PMA is spec compliant across a wide operating junction temperature range (-20 °C to 105 °C). PLLs, bias circuits, and data paths are functional between -40 °C to 125 °C
- In-situ real-time monitoring and receive data eye voltage histogram
- Built in PRBS generators and checkers along with custom pattern generation
- ATPG Mux Scan support for digital logic
- IEEE 1149.6 JTAG boundary scan for SerDes pins
- Built-in BER monitor including a 40-bit counter to count the total number of bits received and a 30-bit counter to count the total number of errors detected by a pattern checker
- Internal serial loopback and parallel loopback support
- Interfaces available for connection to a JTAG TAP controller or through a simple parallel read/write port
- Analog and digital test bus
Benefits
- A 56 GS/s ADC provides extended reach and future scalability
- Configurable architecture enables power savings for low-loss channels
- Analog RX CTLE
- Digital TX/RX FFE and DFE
- Supports Ethernet auto negotiation and link training
- Multiple lane configurations to allow flexible ASIC floorplan integration
- Extensive debug capabilities and interfaces using internal microprocessor
- LabStation™ software and scripts for enhanced bring-up and validation
- Available in advanced 7nm FINFET process node
Deliverables
- PMA Hard Macro and Design Kit
- Verilog models
- LEF abstracts (.lef)
- Timing models (.lib)
- CDL netlists (.cdl)
- ATPG models
- IBIS-AMI models
- GDSII layout
- DRC & LVS reports
- Datasheet
- SoC integration guide
- Optional design integration and bring-up support services
Applications
- 100/200/400/800 GbE interfaces
- 112G chip-to-module (C2M) interfaces
- 112G chip-to-chip (C2C) interfaces
Block Diagram of the 112G LR Multi-protocol SerDes PHY IP Core
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