Symmetric Cryptography Engine: High Performance AES-GCM/CTR IP Core
112Gbps Multi-Rate Long-Reach PAM-4 SerDes
The multi-rate SerDes IP supports true plesiochronous operation at the data rates shown within +/- 200ppm. An integrated microcontroller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).
There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings. The channel estimation hardware allows the accurate measurement of the channel response to assess package, connector, and trace characteristics.
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multi-protocol IP
- 1-56/112G Multi-protocol Serdes (Interlaken, JESD204, CPRI, Ethernet, OIF/CEI)
- Multi-Protocol Crypto Engine
- Multi-Protocol Crypto Engine with Classification
- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
- 32G Medium Reach Multi-Protocol SerDes PHY
- Multi-Protocol Crypto Packet Engine, Low Power, Bus Attached