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180nm FTP Non Volatile Memory for Standard CMOS Logic Process
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112Gbps Multi-Rate Long-Reach PAM-4 SerDes
The Cadence® 112Gbps Multi-Rate Long-Reach PAM-4 SerDes IP supports dual lanes and multiple data rates. The SerDes operates at a full-rate of 112Gbps using PAM-4 modulation and half-rate of 56Gbps using PAM-4 modulation, as well as 56/28/10Gbps using NRZ. This IP enables high-speed communications between chips, backplane, and long-haul optical interconnects by converting between parallel data and extremely high-speed serial data streams with improved signal reliability. The area- and power-optimized design is ideal for high port-density applications that require long-reach and medium-reach links.
The multi-rate SerDes IP supports true plesiochronous operation at the data rates shown within +/- 200ppm. An integrated microcontroller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).
There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings. The channel estimation hardware allows the accurate measurement of the channel response to assess package, connector, and trace characteristics.
The multi-rate SerDes IP supports true plesiochronous operation at the data rates shown within +/- 200ppm. An integrated microcontroller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).
There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings. The channel estimation hardware allows the accurate measurement of the channel response to assess package, connector, and trace characteristics.
Features
- Available 7nm FinFET CMOS Processes
- 112/56Gbps PAM-4 or 56/28/10Gbps NRZ data rates
- Power-optimized for LR and MR links
- Compact footprint for high-density designs
- Fully autonomous startup and adaptation without requiring ASIC intervention
- Integrated BIST capable of producing and checking PRBS
Benefits
- Best-in-class DSP supports long-reach lossy channels
- Small area and low power is ideal for high port-density applications
- Symmetric floorplan allows north-south and east-west SoC orientation
- Comprehensive on-chip diagnostic features make system testing/debugging quick and easy
Deliverables
- GDS II macros with abstract in LEF
- Verilog post-layout netlist
- STA scripts for use at chip or standalone PHY levels
- Verilog and Liberty timing models
- Documentation, including integration, user guide, and release notes
Applications
- High-Performance Computing applications, especially SoCs driving 100G/400G Ethernet ports
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