112Gbps XSR SerDes IP for TSMC 7nm FinFET
The 112G-XSR SerDes IP supports true plesiochronous operation within +/- 200ppm. Each receiver includes clock-data-recovery (CDR) for tracking PPM offset. An integrated micro-controller allows for fully autonomous startup, adaptation, and service operation without requiring ASIC intervention. A programming and observation interface is provided via a parallel bus with MDIO-style addressing (port, device, address).
There are several comprehensive on-chip diagnostic tools that enable testability and easy debugging. A post-equalized histogram is available for accurate estimation of bit error rate (BER) even in the absence of actual bit errors. Vertical eye statistics can be logged to allow optional optimization of the device settings.
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Block Diagram of the 112Gbps XSR SerDes IP for TSMC 7nm FinFET
