The S3ADS2M12BT22ULL is an ultra-compact and lowpower 12-bit SAR ADC IP with a sampling rate up to 1.7MS/s. The ADC can also be reconfigured to 10-bit and 8- bit resolutions.
For application flexibility, this IP includes a Reference Buffer to drive the SAR ADC capacitive DAC.
The input signal sampling time is controlled externally, making this ADC extremely flexible and able to interface with multiple blocks with different output driving strengths. A calibration algorithm enhances the ADC performance.
During calibration, analog inputs are kept in high impedance, therefore relaxing the requirements for the block driving the ADC.
As a 12-bit ADC, it features an outstanding dynamic performance including 63.6dB SNR, 76.0dB SFDR and 10.2-bit ENOB. It also features an outstanding static performance with < ±0.9 LSB DNL (no missing-codes) and < ±1.5 LSB INL. At 1.7MS/s sampling rate, the power dissipation is ultra low, including the Reference Buffer.
The S3ADS2M12BT22ULL can be cost-effectively ported to other process.
- TSMC 22nm ULL Process
- 0.8V Core Supply
- 1.6V to 3.6V I/O Supply
- 12 / 10 / 8 - bit Reconfigurable SAR ADC
- Sampling Rate up to 1.7MS/s (12-bit Mode) &
- 2.8MS/s (8-bit Mode)
- Clock Frequency up to 48MHz
- Configurable Sampling Time
- Input Mux w/ 12 Single-Ended Inputs
- 1.2V External Reference with Internal Buffer
- Input Range: 0V to 1.2V
- Static Performance:
- DNL < ± 0.9 LSB (no Missing-Codes)
- INL < ± 1.5 LSB
- Dynamic Performance:
- 76.0dB SFDR
- 63.6dB SNR
- 63.2dB SNDR
- 10.2-bit ENOB
- Ultra-Low Power Dissipation
- Compact Die Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- Motion and Environmental Sensing
- Temperature Sensing
- Industrial Control
- Home Automation
- Consumer Electronics
- Auxiliary Control
Block Diagram of the 12 / 10 / 8-bit Reconfigurable SAR ADC 1.7MS/s (12-bit Mode) 2.8MS/s (8-bit Mode)