12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++

The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specification with support for PIPE interface spec, Universal Serial Bus (USB) compliant with USB 3.0, USB 2.0 (USB High-speed and Full speed), and Serial ATA (SATA) consistent with SATA 3.0 Specification. Because inbuilt power gating control, reference clock control, and more PLL control are supported, lower power consumption is made possible. Additionally, the PHY is broadly usable for diverse circumstances under varying considerations of power consumption because the aforementioned low
power mode option is customizable.

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