This high-speed Digital-to-Analog Converter (DAC) IP block is implemented with fully differential single channel output specifically designed for crystal drivers and wideband signal handling.
The 12-bit DAC is based on current steering architecture and utilizes segmentation and robust timing control for high-speed operation till 1.2GSps. Typical DAC SFDR is 71dB for a 42MHz output frequency with 67dB of SNR.
Using a small geometry CMOS process, the monolithic DAC is designed to operate within a single-supply range of 1.6V to 3.3V. It provides programmable control to tune the output current range and power consumption.
- Differential, 12-bit, 1.2GSps current-steering DAC
- Optimized for 2ps signal delay variation over 10°C
- Programmable gain
- Built-in LDOs with >25dB PSRR across all frequencies
- Built-in sleep mode
- Wide temperature operation (-40°C to 115°C)
- 1.6V to 3.3V supply operation
- TSMC 40nm CMOS (1P7M)
- Wideband signal handling
- 2ps signal delay variation
- Design deliverables:
- Schematics and layouts of the IP sub-blocks
- Verilog-A model of the IP sub-blocks
- Simulation states and full suite of test benches in Cadence
- Design documents including block level documentation
- Crystal drivers
- Timing applications Wideband signal processing