The S3DAIQ1G312BT12 employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture and randomization of the output current sources.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit Dual DAC features an excellent static performance that includes ±0.8LSB DNL and ±2.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 26MHz and 1.3GS/s conversion rate include an SNR > 68dB and an SFDR > 60dBc.
The S3DAIQ1G312BT12 is designed in a 12nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.