12-bit 8 MS/s ADC contains Charge redistribution DAC, Successive Approximation Logic, Comparator. ADC based on successive approximation architecture. The sub-ranging and output offset compensation techniques for reduce size area and improve linearity in relatively are used. The common-centroid matching technique and dummy capacitors to improve matching of capacitors and to reduce static nonlinearity are used. ADC requires: 2.25 ÷2.75 V supply, reference current 9.9 ÷ 10.1 uA; differential reference voltage 0.75 V and 1.25 V; common-mode voltage 1.25 V; differential input clock with duty cycle 45 ÷ 55 %. The blocking capacitors for reference voltages should be added. ADC supports standby mode. There is also the ability to configure the operating modes of the ADC with digital registers: ST1_CC<2:0> and ST2_CC<2:0> adjust current of pre-amplifiers Comparator. These are allows to reduce power dissipation with reducing sampling rate or dynamic and static parameters.
There is opportunity on base 12-bit 8 MS/s to design time-interleaved ADC with sampling rate 100MS/s without Phase-Locked Loop (PLL). This is allows to reduce complexity of design high speed ADC and reduce power dissipation.
The block is designed on TSMC CMOS 65 nm technology.