The S3DAIQ100M12BT40LPA employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- 40nm TSMC Logic LP Process, 6 Metals Used (4X1Z, with M6 as 4XTM)
- 2.5V and 1.1V Supplies
- Sampling Rate up to 100MHz
- Programmable Voltage Output or Current Output
- DNL< 1LSB Typ.; INL< 1.5LSB
- High Performance at 100MHz clock rate
- SNDR = 66dB, SFDR = 70dB, Fout= 10MHz
- Stand-By and Power-Down Modes
- This 12-bit dual DAC features an excellent static performance that includes ±1LSB DNL and ±1.5LSB INL.
- Dynamic performance highlights considering a signal frequency with 10MHz and 100MHz conversion rate include an SNDR of 66dB and an SFDR of 70dBc.
- The S3DAIQ100M12BT40LPA is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- The DAC block support either current or voltage outputs. The voltage outputs are generated by a set of internal reference resistors which generate either a maximum 1.0Vpk-pk or 0.8Vpk-pk differential output swing signal.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- WiFi 802.11X, WiMAX 802.16x
- LTE, GSM
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 100MHz Dual Current Steering DAC