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12-Bit 125MS/s Dual DAC
The S3DAIQ125M12BT65 employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1LSB INL.
Dynamic performance highlights considering a signal frequency with 10MHz and 125MS/s conversion rate include an SNR of 66dB and an SFDR of 71dBc.
The S3DAIQ125M12BT65 is designed in a 65nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This 12-bit dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1LSB INL.
Dynamic performance highlights considering a signal frequency with 10MHz and 125MS/s conversion rate include an SNR of 66dB and an SFDR of 71dBc.
The S3DAIQ125M12BT65 is designed in a 65nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
Features
- 65nm TSMC Logic LP Process, 6 Metals Used
- No Analog Options
- 2.5V and 1.2V Supplies
- Sampling Rate up to 125MS/s
- 1.0Vpp Differential Output Range
- 30mW Power Dissipation at 5mA Output Current
- DNL< 0.5LSB Typ.; INL< 1LSB Typ.
- High Performance at 125MS/s
- SNR = 68dB, SFDR = 71dB, Fout= 10MHz
- Stand-By and Power-Down Modes
- Compact Die Area
Applications
- DVB-C, DOCSIS
- WiFi 802.11X, WiMAX 802.16x
- Video
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 125MS/s Dual DAC IP Core
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