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12-bit 160MS/s ADC
The S3ADS160M12BT65LP is a low-power 12-bit High-Speed SAR ADC IP.
This 12-bit ADC, working at 160MS/s sampling rate, features an excellent performance including 75.0dB SFDR, -75.0dB THD, 63.5dB SNR and 10.2-bit ENOB (noise integrated up-to Nyquist).
This high-end performance is obtained while dissipating below 20mW.
A built-in calibration algorithm enhances the ADC performance and for additional flexibility, an I2C interface is available to read in/out the calibration coefficients.
This 12-bit ADC, working at 160MS/s sampling rate, features an excellent performance including 75.0dB SFDR, -75.0dB THD, 63.5dB SNR and 10.2-bit ENOB (noise integrated up-to Nyquist).
This high-end performance is obtained while dissipating below 20mW.
A built-in calibration algorithm enhances the ADC performance and for additional flexibility, an I2C interface is available to read in/out the calibration coefficients.
Features
- TSMC 65nm LP (Low Power Process)
- 1.2V Supply
- 12-bit High-Speed SAR ADC
- Sampling Rate up-to 160MS/s
- Differential Input Signal Range: 1.2Vppdiff
- Outstanding Dynamic Performance:
- 75.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.1dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Built-In Calibration
- I2C Interface for Calibration Codes Read In/Out
- Low Power Dissipation: Only 20mW
Benefits
- The S3ADS160M12BT65LP can be cost-effectively ported across foundries and process nodes upon request
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
Applications
- Satellite Communication Applications
- Wireless Communications
- Wireline Communications
- Imaging
Block Diagram of the 12-bit 160MS/s ADC IP Core
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