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12-Bit 160MS/s Dual Current Steering DAC
The S3DAIQ160M12BGF28 employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
Features
- 28nm Global Foundries SLP Process, 7 Metals Used
- 1.8V and 1.0V Supplies
- Sampling Rate up to 160MS/s
- 1.0Vpp Differential Output Range
- DNL= 0.5LSB; INL<2.0LSB.Typ
- High Performance for Fout=10MHz
- SNR= 69dB, SFDR=70dB
- Stand-By and Power-Down Modes
- 11mW Power consumption at 2mA Output current
- Compact Die Area pre-shrink: 0.2mm2
Benefits
- This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±2.0LSB INL for typical conditions.
- Dynamic performance highlights considering a signal frequency of 10MHz and 160MS/s conversion rate include an SNR= 69dB and an SFDR=70dBc.
- The S3DAIQ160M12BGF28 is designed for operation up to 160MS/s. The S3DAIQ160M12BGF28 is designed in a 28nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
Applications
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 160MS/s Dual Current Steering DAC
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