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12-Bit 160MS/s Dual Current Steering DAC
The S3DAIQ160M12BT40ULP employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 160MS/s conversion rate include an SNR= 68dB and an SFDR=70dBc.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 160MS/s conversion rate include an SNR= 68dB and an SFDR=70dBc.
Features
- 40nm TSMC ULP Process, 7 Metals Used
- 1.8V and 1.1V Supplies
- Sampling Rate up to 160MS/s
- 1.0Vpp Differential Output Range
- DNL= 0.5LSB; INL<1.0LSB.Typ
- High Performance for Fout=10MHz
- SNR> 68dB, SFDR=70dB
- In-band SFDR=75dB with Fout=10MHz
- Stand-By and Power-Down Modes
- 9mW Power Consumption at 2mA output current
- Compact Die Area pre-shrink: 0.225mm2
Benefits
- The S3DAIQ160M12BT40ULP is designed for operation up to 160MS/s. The S3DAIQ160M12BT40ULP is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
Applications
- LTE/Mobile
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 160MS/s Dual Current Steering DAC
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