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12-bit 200MS/s ultra-efficient SAR ADC in UMC 28nm
The S3ADSIQ200M12BC28HPC is an ultra low-power 12-bit dual-channel High-Speed SAR ADC IP.
With a sampling rate of 200MS/s per channel, this 12-bit ADC features an excellent dynamic performance including -75.0dB THD, 63.5dB SNR and 10.2-bit ENOB (noise integrated up-to Nyquist bandwidth, including References circuitry noise contribution). It also features an excellent cross-channel performance including I/Q Crosstalk better than -75.0dB.
With a sampling rate of 200MS/s per channel, this 12-bit ADC features an excellent dynamic performance including -75.0dB THD, 63.5dB SNR and 10.2-bit ENOB (noise integrated up-to Nyquist bandwidth, including References circuitry noise contribution). It also features an excellent cross-channel performance including I/Q Crosstalk better than -75.0dB.
Features
- UMC 28nm HPC Process
- 0.9V & 1.8V Supplies
- 12-bit High-Speed SAR Dual-Channel ADC
- 200MS/s Sampling Rate per Channel
- Internal Bandgap and Biasing System Included
- All required Voltage References Included
- No External Accurate Reference required
- No External Reference Decoupling required
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 75.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.2dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Outstanding I/Q Cross-Channel
- Performance:
- < ±0.1dB I/Q Channels Gain Mismatch
- < -75.0dB Crosstalk between I/Q Channels
Benefits
- Robust Performance
- Low Power
- Low Area
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (VHDL/Verilog .v)
- Integration Guidelines and Support
Applications
- Connected Consumer Devices
- LTE
- 802.11n/ac/ax
- DVB
- Home Network
- Wireless & Wireline Communications Infrastructure
- Wireline Communications
- Imaging
Block Diagram of the 12-bit 200MS/s ultra-efficient SAR ADC in UMC 28nm
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