12-bit 200MS/s ultra-efficient SAR ADC in UMC 28nm

Features

• UMC 28nm HPC Process
• 0.9V & 1.8V Supplies
• 12-bit High-Speed SAR Dual-Channel ADC
• 200MS/s Sampling Rate per Channel
• Internal Bandgap and Biasing System Included
• All required Voltage References Included
• No External Accurate Reference required
• No External Reference Decoupling required
• Differential Input Signal Range: 1.0Vppdiff
• Outstanding Dynamic Performance:
• 75.0dB SFDR
• -75.0dB THD
• 63.5dB SNR
• 63.2dB SNDR
• 10.2-bit ENOB
• [Noise integrated up-to Nyquist]
• Outstanding I/Q Cross-Channel
• Performance:
• < ±0.1dB I/Q Channels Gain Mismatch
• < -75.0dB Crosstalk between I/Q Channels
• Ultra Low Power Dissipation: 20mW
• Ultra Compact Die Area: 0.12mm2

Benefits

• This high-end performance is obtained with an ultra
• compact die area of 0.12mm2 and dissipating a mere
• 20mW at 200MS/s for the complete Dual-Channel ADC
• including internal references.
• The S3ADSIQ200M12BC28HPC can be cost-effectively
• ported across foundries and process nodes upon request

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioral Model (VHDL/Verilog .v)
• Integration Guidelines and Support

Applications

• Connected Consumer Devices
• LTE
• 802.11n/ac/ax
• DVB
• Home Network
• Wireless & Wireline Communications Infrastructure
• Wireline Communications
• Imaging

Block Diagram of the 12-bit 200MS/s ultra-efficient SAR ADC in UMC 28nm

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