The 12-Bit ADC is re-configurable as a Single Time-Interleaved ADC with sampling rate of 250MS/s or as a Dual Input ADC with sampling rate of 125MS/s per channel.
The 12-Bit ADC employs a high-performance input buffer (IB), sample-and-hold (S/H) circuit and pipeline ADC architecture.
The S/H circuit features an analog input bandwidth higher than 500MHz and can operate in under sampling mode for communications applications.
For maximum flexibility, the power dissipation of the ADC scales with the sampling frequency.
The IF Mode 12-Bit ADC features an excellent static performance that includes ±0.75LSB DNL and ±3.0LSB INL typically. Dynamic performance highlights considering an Un-Buffered 10MHz input signal, 250MS/s sampling rate, include SNR of 65dB, SFDR of 73dB and SNDR of 64dB, yielding an outstanding 10.3ENOB performance.
The BB Mode 12-Bit ADC features an excellent static performance that includes ±0.5LSB DNL and ±2.5LSB INL typically. Dynamic performance highlights considering an 10MHz input signal, 125MS/s sampling rate per channel, include SNR of 67dB, SFDR of 76dB and SNDR of 65dB, yielding an outstanding 10.5ENOB performance.
Auxiliary circuits comprising a bandgap, frequency-dependent current biasing and internal reference buffers are also included.
The 12-bit 250MS/s ADC does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
- 65nm TSMC CMOS LP Logic Process
- 1.2V and 2.5V Power Supply
- Re-Configurable to be a:
- Single 12-Bit ADC operating at up to Fs=250MS/s
- Dual 12-Bit ADC operating at up to Fs=125MS/s per channel
- 1Vpp Differential Input Range
- SNR @ FIN = 10MHz (Typical)
- Dual 12-Bit ADC: 65dB (Un-Buffered)
- Single 12-Bit ADC: 67dB
- SNDR @ FIN = 10MHz (Typical)
- Dual 12-Bit ADC: 64dB; 10.3 ENOB (Un-Buffered)
- Single 12-Bit ADC: 65dB; 10.5 ENOB
- SFDR @ FIN = 10MHz (Typical)
- Dual 12-Bit ADC: 73dB (Un-Buffered)
- Single 12-Bit ADC: 76dB
- Stand-By and Power Down Modes
- Compact Die Area
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
- Mobile Communications: HSPA, LTE
- WiFi, WiMax
- Powerline Communications
- DOCSIS, MoCA, DVB-C
Block Diagram of the 12-bit 250MS/s ADC IP Core