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12-bit 250MS/s Dual IQ High-Speed SAR ADC - TSMC 12nm FFC
The S3ADSIQ250M12BT12FFCB is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP.
This IP includes two ADC channels sampling up-to 250MS/s including Voltage Reference Buffers. It features an excellent dynamic performance including 70.0dB SFDR, 63.4dB SNR and 10.1-bit ENOB. It also features an excellent crosschannel performance with ±0.1dB Gain Mismatch and - 70.0dB Crosstalk.
This high-end performance is obtained with a compact die area and dissipating a ultra low power for the full IP, including both channels converting continuously at 250MS/s.
The S3ADSIQ250M12BT12FFCB can be cost-effectively ported across foundries and process nodes.
This IP includes two ADC channels sampling up-to 250MS/s including Voltage Reference Buffers. It features an excellent dynamic performance including 70.0dB SFDR, 63.4dB SNR and 10.1-bit ENOB. It also features an excellent crosschannel performance with ±0.1dB Gain Mismatch and - 70.0dB Crosstalk.
This high-end performance is obtained with a compact die area and dissipating a ultra low power for the full IP, including both channels converting continuously at 250MS/s.
The S3ADSIQ250M12BT12FFCB can be cost-effectively ported across foundries and process nodes.
Features
- TSMC 12nm FFC Process
- 0.8V and 1.8V Supplies
- 12-bit Dual-Channel High-Speed SAR ADC
- Sampling Rate per Channel up-to 250MS/s
- Reference Buffers Included
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 70.0dB SFDR
- 63.4dB SNR
- 62.5dB SNDR
- 10.1-bit ENOB
- [Noise integrated up-to Nyquist]
- Outstanding Cross-Channel Performance:
- < ±0.1dB Channels Gain Mismatch
- < -70.0dB Crosstalk between Channels
- Ultra Low Power Dissipation: both channels converting at 250MS/s)
- Ultra Compact Silicon Die Area
Benefits
- The ADC does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
- Available now on 16nm and 12nm.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (tlf)
- Behavioral Model (VHDL/Verilog)
- Integration Support
Applications
- Sub-6GHz 5G Wireless Communications
- 802.11ax
- Wireline Infrastructure Communications
- Next Generation DSL
- Imaging
Block Diagram of the 12-bit 250MS/s Dual IQ High-Speed SAR ADC - TSMC 12nm FFC
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