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12-bit 2MS/s ADC
The S3ADS2M12BT55ULP is an ultra-low power 12-bit SAR ADC IP with a sampling rate up to 2MS/s.
At 2MS/s sampling rate, this 12-bit ADC features an outstanding dynamic performance that includes -75.0dB THD, 65.4dB SNR and 10.5-bit ENOB.
It also features an outstanding static performance with =< ±0.9 LSB DNL (no missing-codes) and < ±1.5 LSB INL.
At 2MS/s sampling rate, this 12-bit ADC features an outstanding dynamic performance that includes -75.0dB THD, 65.4dB SNR and 10.5-bit ENOB.
It also features an outstanding static performance with =< ±0.9 LSB DNL (no missing-codes) and < ±1.5 LSB INL.
Features
- TSMC 55nm ULP Embedded-Flash
- No Analog Options
- 3.3V and 1.2V Supplies
- 12-bit SAR ADC
- Sampling Rate up to 2MS/s
- External Reference VREF: 2.0V up to 3.6V
- Input Signal Range: 0 to VREF
- Gain Error < 1%
- Input Referred Offset < 1%
- Static Performance:
- DNL < ±0.9 LSB (no Missing-Codes)
- INL < ±1.5 LSB
- Dynamic Performance:
- 76.0dB SFDR
- -75.0dB THD
- 65.4dB SNR
- 65.0dB SNDR
- 10.5-bit ENOB
- [Noise integrated up-to Nyquist]
- Ultra-Low Power Dissipation: <350uA Total Supply Current
- Ultra-Compact Die Area: 0.05mm2 (post optical shrink)
Benefits
- This high-end performance is obtained with <350uA total Supply Current during ADC conversion.
- The S3ADS2M12BT55ULP can be cost-effectively ported across foundries and process nodes upon request.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
Applications
- Motion and Environmental Sensing
- Automotive Applications
- Industrial Control
- Home Automation
- Consumer Electronics
- Auxiliary Control
Block Diagram of the 12-bit 2MS/s ADC IP Core
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