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800MHz, 12-bit High Speed Delta Sigma ADC for 5G, LiDAR and Imaging
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12-bit 2MS/s Dual Input ADC
The S3AD2M12BCF18 is a low-power, dual input, reconfigurable 12/10-bit ADC IP dissipating 7.4mW and 10.6mW over a single 1.8V supply, respectively for 12-bit mode and 1.7MS/s sampling rate and 10-bit mode and 3.4MS/s.
The ADC employs two high-performance front-end sample-and-hold (S/H) circuits sampling simultaneously two different inputs together with a two-stage algorithmic architecture and digital error correction. The two inputs can be either single-ended or differential. The S/H features an analog input bandwidth higher than 24MHz and can operate in under-sampling mode.
In 12-bit mode at 1.7MS/s, the ADC features an excellent static performance that includes ±0.6LSB DNL and ±1.75LSB INL.
Dynamic performance highlights considering an input signal with 1MHz frequency and 1.7MS/s sampling rate include an SNR of 56.5dB and a typical ENOB of 9.1-bit.
Auxiliary circuits comprising a low-noise bandgap reference, voltage reference buffers and on-chip current biasing are also included to provide a complete ADC solution.
The S3AD2M12BCF18 is implemented in 0.18um Mixed Signal Generic process with Embedded Flash Option using MiM capacitors and DNW, occupies a total die area of only 0.25mm2 and can be cost-effectively ported across foundries and process nodes upon request.
The ADC employs two high-performance front-end sample-and-hold (S/H) circuits sampling simultaneously two different inputs together with a two-stage algorithmic architecture and digital error correction. The two inputs can be either single-ended or differential. The S/H features an analog input bandwidth higher than 24MHz and can operate in under-sampling mode.
In 12-bit mode at 1.7MS/s, the ADC features an excellent static performance that includes ±0.6LSB DNL and ±1.75LSB INL.
Dynamic performance highlights considering an input signal with 1MHz frequency and 1.7MS/s sampling rate include an SNR of 56.5dB and a typical ENOB of 9.1-bit.
Auxiliary circuits comprising a low-noise bandgap reference, voltage reference buffers and on-chip current biasing are also included to provide a complete ADC solution.
The S3AD2M12BCF18 is implemented in 0.18um Mixed Signal Generic process with Embedded Flash Option using MiM capacitors and DNW, occupies a total die area of only 0.25mm2 and can be cost-effectively ported across foundries and process nodes upon request.
Features
- TSMC 0.18 um Mixed Signal G process with Embedded Flash Option (CE018FF)
- Single 1.8V Supply
- Two-Stage Algorithmic ADC Technology
- Programmable 10-bit or 12-bit Resolution
- 0.71-to-2MS/s Sampling Rate at 12-bit Resolution
- 0.85-to-4MS/s Sampling Rate at 10-bit Resolution
- Two Multiplexed Single-Ended or Differential Inputs Sampled Simultaneously
- 1.5Vpp Single-Ended or 3Vpp Differential Input Range
- Low Power Dissipation:
- 7.4mW at 1.7MS/s in 12-bit Mode (12MHz clock)
- 10.6mW at 3.4MS/s in 10-bit Mode (24MHz clock)
- DNL= ±0.6LSB Typ. in 12-bit Mode
- INL= ±1.75LSB Typ. in 12-bit Mode
- SNR= 56.5dB at Fin= 1MHz, 12-bit Mode @1.7MS/s
- Stand-By and Power-Down Modes
- Compact Die Area
Applications
- General Purpose Data Acquisition
Block Diagram of the 12-bit 2MS/s Dual Input ADC
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