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IP Prototyping Kit for DWC UFS 2.X host controller on HAPS-DX7, M-PHY card, PCIe connection for PC
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12-bit 2MS/s SAR ADC - TSMC, 110nm
The S3ADS2M12BT110 is an ultra-low power 12-bit SAR ADC IP with a sampling rate up to 2MS/s. The ADC includes an input multiplexer with 33 analog Single-Ended inputs.
At 2MS/s sampling rate, this 12-bit ADC features an outstanding dynamic performance that includes 65.4dB SNR and 10.5-bit ENOB.
It also features an outstanding static performance with < ±0.9 LSB DNL (no missing-codes) and < ±1.5 LSB INL.
The input signal sampling time is controlled externally, which makes this ADC very flexible and able to interface with multiple blocks with different output driving strengths.
This high-end performance is obtained with <500uA Supply Current during ADC conversion. In Idle mode, the ADC has no Power Dissipation and it is immediately ready for new conversions, not requiring any Wake-Up time.
At 2MS/s sampling rate, this 12-bit ADC features an outstanding dynamic performance that includes 65.4dB SNR and 10.5-bit ENOB.
It also features an outstanding static performance with < ±0.9 LSB DNL (no missing-codes) and < ±1.5 LSB INL.
The input signal sampling time is controlled externally, which makes this ADC very flexible and able to interface with multiple blocks with different output driving strengths.
This high-end performance is obtained with <500uA Supply Current during ADC conversion. In Idle mode, the ADC has no Power Dissipation and it is immediately ready for new conversions, not requiring any Wake-Up time.
Features
- TSMC 110nm G Process
- No Analog Options
- 3.3V Analog and 1.2V Digital Supplies
- 12-bit SAR ADC
- Sampling Rate up to 2MS/s
- Power Scales with Sampling Rate
- Programmable Sampling Time
- 33 MUX Single-Ended Inputs
- Input Signal Range: 0V to AVDD
- Static Performance:
- DNL < ±0.9 LSB (no Missing-Codes)
- INL < ±1.5 LSB
- Dynamic Performance:
- 76.0dBc SFDR
- -75.0dB THD
- 65.4dB SNR
- 10.5-bit ENOB
- ADC Conversion and Idle Modes
- Idle Mode:
- No Power Dissipation
- No Wake-Up Time
- Ultra Low Power Dissipation:
- <500uA Supply Current during ADC Conversion
- Compact Die Area: 0.16mm2
Benefits
- The S3ADS2M12BT110 does not require any special analog options and can be cost-effectively ported across foundries and process nodes upon request.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioral Model (Verilog)
- Integration Support
Applications
- Motion and Environmental Sensing
- Automotive Applications
- Industrial Control
- Home Automation
- Consumer Electronics
- Auxiliary Control
Block Diagram of the 12-bit 2MS/s SAR ADC - TSMC, 110nm
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