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12-bit 300MS/s Dual Channel IQ DAC in Samsung 8nm LPP
The S3DAIQ300M12BS8LPP employs a current steering
architecture with differential current outputs. It uses 6 linear
bits and 6 binary bits, all of which are generated from within
the current source array.
This segmentation results in an excellent static performance
and reduced glitch energy at the output. This also ensures
parasitics within the DAC are minimized. Furthermore, the
distortion at the output is greatly reduced by using propriety
latch architecture and randomization of the output current
sources. The combination of static performance, reduced
glitch energy, minimized parasitics and reduced distortion,
results in outstanding dynamic performance over a wide
range of conditions including frequencies close to the DAC
Nyquist frequency.
This 12-bit Dual DAC features an excellent static
performance that includes ±0.8LSB DNL and ±1.5LSB INL for
typical conditions.
Dynamic performance, considering a signal frequency of
10MHz and 302MS/s conversion rate include an SNR > 68dB
and an SFDR > 70dBc. The S3DAIQ300M12BS8LPP is
designed for operation up to 302MS/s. The
S3DAIQ300M12BS8LPP is designed in a 8nm logic process,
which is ideal for integration with a DSP engine,
and can be cost-effectively ported across foundries and
process nodes upon request.
architecture with differential current outputs. It uses 6 linear
bits and 6 binary bits, all of which are generated from within
the current source array.
This segmentation results in an excellent static performance
and reduced glitch energy at the output. This also ensures
parasitics within the DAC are minimized. Furthermore, the
distortion at the output is greatly reduced by using propriety
latch architecture and randomization of the output current
sources. The combination of static performance, reduced
glitch energy, minimized parasitics and reduced distortion,
results in outstanding dynamic performance over a wide
range of conditions including frequencies close to the DAC
Nyquist frequency.
This 12-bit Dual DAC features an excellent static
performance that includes ±0.8LSB DNL and ±1.5LSB INL for
typical conditions.
Dynamic performance, considering a signal frequency of
10MHz and 302MS/s conversion rate include an SNR > 68dB
and an SFDR > 70dBc. The S3DAIQ300M12BS8LPP is
designed for operation up to 302MS/s. The
S3DAIQ300M12BS8LPP is designed in a 8nm logic process,
which is ideal for integration with a DSP engine,
and can be cost-effectively ported across foundries and
process nodes upon request.
Features
- 8nm Samsung LPP Process, 7 Metals Used
- 1.8V and 0.75V Supplies
- Sampling Rate up to 302MS/s
- 0.75Vpp Differential Output Range
- DNL< 1.0LSB; INL<2.0LSB.
- High Performance for Fout<20MHz
- SNR > 68dB, SFDR > 70dB
- ENOB>10bits
- In-band SFDR=74dB with Fout=20MHz
- IM3>-69dBc @20MHz
- Stand-By and Power-Down Modes
- Ultra-Low Power Dissipation
- Compact Die Area
Benefits
- Ultra-Low Power Dissipation:
- Compact Die Area:
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
Applications
- Sub-6GHz 5G Wireless Communications
- Wireline Infrastructure Communications
- Next Generation DSL
- G.Fast
- Imaging
Block Diagram of the 12-bit 300MS/s Dual Channel IQ DAC in Samsung 8nm LPP
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