The S3DAIQ325M12BSM55LL employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture.
This 12-bit Dual DAC features an excellent static performance that includes ±0.5LSB DNL and ±1.0LSB INL for typical conditions.
Dynamic performance highlights considering a signal frequency of 10MHz and 325MS/s conversion rate include an SNR= 68dB and an SFDR=70dBc.
- 55nm SMIC LL Process, 6 Metals Used
- 3.3V and 1.2V Supplies
- Sampling Rate up to 325MS/s
- 2.6Vpp Differential Output Range
- DNL= 0.5LSB; INL<1.0LSB.Typ
- High Performance for Fout=10MHz
- Stand-By and Power-Down Modes
- 24mW Power Consumption at 2.5mA output current
- Die Area pre-shrink: 0.505mm2
- The S3DAIQ325M12BSM55LL is designed for operation up to 325MS/s. The S3DAIQ325M12BSM55LL is designed in a 55nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 325MS/s Dual Current Steering DAC - SMIC 55nm LL