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12-bit 32MS/s Dual-Channel ADC
The S3ADSIQ32M12BT40LP is an ultra low-power, 12-bit Dual-Core High-Speed SAR ADC IP.
This IP includes 2 ADC Channels sampling at 32MS/s. It features an excellent dynamic performance including -75.0dB THD and 10.2-bit ENOB. It also features an excellent cross-channel performance with < 0.2dB Gain Mismatch and -75.0dB Crosstalk.
This high-end performance is obtained with a compact die area of 0.13mm2 and dissipating a mere 7.5mW for the complete IP.
This IP includes 2 ADC Channels sampling at 32MS/s. It features an excellent dynamic performance including -75.0dB THD and 10.2-bit ENOB. It also features an excellent cross-channel performance with < 0.2dB Gain Mismatch and -75.0dB Crosstalk.
This high-end performance is obtained with a compact die area of 0.13mm2 and dissipating a mere 7.5mW for the complete IP.
Features
- TSMC 40nm LP Process
- No Analog Options
- 1.1V Core & 2.5V I/O Supplies
- 12-bit High-Speed SAR Dual-Channel ADC
- 32MS/s Sampling Rate per ADC Core
- Input Clock: 32MHz
- Internal Bandgap and Biasing System Included
- All required Voltage References Included
- No External Accurate Reference required
- No External Reference Decoupling required
- Good Power-Supply Noise Rejection
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 75.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.1dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Outstanding I/Q Cross-Channel Performance:
- 0.2dB I/Q Channels Gain Mismatch
- -75.0dB Crosstalk between Channels
- Ultra Low Power Dissipation: 7.5mW
- (Complete Dual-Channel ADC incl. References)
- Compact Die Area: Only 0.13mm2
Benefits
- The S3ADSIQ32M12BT40LP does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog)
- Integration Support
Applications
- Connected Consumer Devices
- DVB
- Home Network
- Wireless & Wireline Communications
- Imaging
Block Diagram of the 12-bit 32MS/s Dual-Channel ADC IP Core
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