The S3DAIQ380M12BSM40LL employs a current steering architecture with differential current outputs. It uses 6 linear bits and 6 binary bits, all of which are generated from within the current source array.
This segmentation results in an excellent static performance and reduced glitch energy at the output. This also ensures parasitics within the DAC are minimized. Furthermore, the distortion at the output is greatly reduced by using propriety latch architecture and randomization of the output current sources.
The combination of static performance, reduced glitch energy, minimized parasitics and reduced distortion, results in outstanding dynamic performance over a wide range of conditions including frequencies close to the DAC Nyquist frequency.
- 40nm SMIC LL Process, 6 Metals Used
- 2.5V and 1.1V Supplies
- Sampling Rate up to 380MS/s
- 1.5Vpp Differential Output Range
- DNL< 1.0LSB; INL<2.0LSB.
- High Performance for Fout<64MHz
- SNR > 68dB, SFDR > 60dB,ENOB>10bits
- 30mW Power consumption at 5mA Output current
- Stand-By and Power-Down Modes
- Area pre-shrink: 0.226mm2
- This 12-bit Dual DAC features an excellent static performance that includes ±0.8LSB DNL and ±1.5LSB INL for typical conditions.
- A bias/bandgap is included for easy integration. Dynamic performance highlights considering a signal frequency of 64MHz and 380MS/s conversion rate include an SNR > 68dB and an SFDR > 60dBc.
- The S3DAIQ380M12BSM40LL is designed in a 40nm logic process, which is ideal for integration with a DSP engine, and can be cost-effectively ported across foundries and process nodes upon request.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- *Subject to Agreement
- WiFi 802.11x, WiMAX 802.16x
- Wireline communications
- Direct Digital Synthesis
Block Diagram of the 12-Bit 380MS/s Dual Current Steering DAC