Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circuits. ADC employs a high-performance differential pipeline architecture. There are two operating mode with external and programmable internal references voltages. LVDS receiver supports rail to rail input range.
Quad-channel ADC requires: 1.08 ÷ 1.32 V analog supply and 1.08 ÷ 1.32 V digital supply.
LVDS receiver requires: 2.375 ÷ 2.625 V analog supply, 1.08 ÷ 1.32 V digital supply, differential input clock with duty cycle 45 ÷ 55 %.
Reference current block requires: reference current 9.9 ÷ 10.1 uA.
Reference voltages block requires external capacitors on pins «refp», «refz» and «refn».
Quad-channel ADC supports standby mode which allows state with minimum power consumption.
Each channel can be individually configured into operating mode. Parallel output is used.
The block is designed on TSMC CMOS 65 nm technology.