12-bit 4MS/s ADC

Features

• TSMC 22nm ULL Process
• No Analog Options
• 0.8V Core Supply
• 1.7V to 3.6V I/O Supply
• 12-bit SAR ADC
• Sampling Rate up to 4MS/s
• Input Mux w/ 8 Single-Ended Inputs
• 1.2V External Reference with Internal Buffer
• Input Range: 0V to 1.2V
• Static Performance:
• DNL < ± 0.9 LSB (no Missing-Codes)
• INL < ± 1.5 LSB
• Dynamic Performance:
• 76.0dB SFDR
• 63.6dB SNR
• 63.2dB SNDR
• 10.2-bit ENOB
• Standby and Power-Down Modes
• Ultra-Low Power Dissipation: 750uW
• Compact Die Area: 0.05mm2
• (post-shrink silicon area)

Benefits

• For application flexibility, this IP includes a Reference Buffer to drive the SAR ADC capacitive DAC.
• Considering a 4MS/s sampling rate, the ADC power dissipation is only 750uW, including the Reference Buffer.
• A calibration algorithm enhances the ADC performance. During calibration, analog inputs are kept in high impedance, therefore relaxing the requirements for the block driving the ADC.
• The S3ADS4M12BT22ULL can be cost-effectively ported across foundries and process nodes upon request.

Deliverables

• Datasheet
• Characterization Report
• Flat Netlist (cdl)
• Layout View (gds2)
• Abstract View (lef)
• Timing View (lib)
• Behavioural Model (Verilog .v)
• Integration Guidelines and Support
• *Subject to Agreement

Applications

• Motion and Environmental Sensing
• Temperature Sensing
• Industrial Control
• Home Automation
• Consumer Electronics
• Auxiliary Control

Block Diagram of the 12-bit 4MS/s ADC IP Core

• see the entire 12-bit 4MS/s ADC datasheet
• get in contact with 12-bit 4MS/s ADC Supplier