The S3ADSIQ500M12BS8LPP is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP.
This IP includes two ADC Channels sampling up-to 500MS/s. It features an excellent dynamic performance including - 75.0dB THD, 63.5dB SNR and 10.2-bit ENOB. It also features an excellent cross-channel performance with ±0.1dB Gain Mismatch and -75.0dB Crosstalk.
This high-end performance is obtained with a compact die area and low power dissipating with both channels converting continuously at 500MS/s.
The S3ADSIQ500M12BS8LPP can be cost-effectively ported across foundries and process nodes upon request.
- Samsung 8nm LPP Process
- 0.75V and 1.8V Supplies
- 12-bit High-Speed SAR Dual-Channel ADC
- Sampling Rate per Channel up-to 500MS/s
- Power Scaling with Sampling Rate
- Input Buffers Included
- Internal Bandgap and Voltage Reference Buffers Included.
- No External Accurate Reference required
- No External Reference Decoupling required
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance: o 75.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.1dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Outstanding Cross-Channel Performance:
- < ±0.1dB Channels Gain Mismatch
- < -75.0dB Crosstalk between Channels
- Ultra-Low Power Dissipation:
- Compact Die Area:
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
- Sub-6GHz 5G Wireless Communications
- Wireline Infrastructure Communications
- Next Generation DSL
Block Diagram of the 12-bit 500MS/s Dual Channel IQ ADC