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The S3ADSIQ500M12BT16FFC is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP.
This IP includes two ADC channels sampling up-to 500MS/s including Input Buffers and Voltage Reference Buffers. It features an excellent dynamic performance including 70.0dB SFDR, 63.4dB SNR and 10.1-bit ENOB. It also features an excellent cross-channel performance with ±0.1dB Gain Mismatch and -70.0dB Crosstalk.
This high-end performance is obtained with a compact die area and dissipating mere mW for the full IP, including both channels converting continuously at 500MS/s. The S3ADSIQ500M12BT16FFC can be cost-effectively ported across foundries and process nodes.
12-bit 500MS/s Dual Channel IQ ADC
The S3ADSIQ500M12BT16FFC is an ultra low power 12-bit dual-channel High-Speed SAR ADC IP.
This IP includes two ADC channels sampling up-to 500MS/s including Input Buffers and Voltage Reference Buffers. It features an excellent dynamic performance including 70.0dB SFDR, 63.4dB SNR and 10.1-bit ENOB. It also features an excellent cross-channel performance with ±0.1dB Gain Mismatch and -70.0dB Crosstalk.
This high-end performance is obtained with a compact die area and dissipating mere mW for the full IP, including both channels converting continuously at 500MS/s. The S3ADSIQ500M12BT16FFC can be cost-effectively ported across foundries and process nodes.
Features
- TSMC 16nm FFC Process
- 0.8V and 1.8V Supplies
- 12-bit Dual-Channel High-Speed SAR ADC
- Sampling Rate per Channel up-to 500MS/s
- Input Buffers and Reference Buffers Included
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 70.0dB SFDR
- 63.4dB SNR
- 62.5dB SNDR
- 10.1-bit ENOB
- [Noise integrated up-to Nyquist]
- Outstanding Cross-Channel Performance:
- < ±0.1dB Channels Gain Mismatch
- < -70.0dB Crosstalk between Channels
- Ultra Low Power Dissipation:
- Ultra Compact Silicon Die Area:
Benefits
- Outstanding Dynamic Performance:
- Ultra Low Power Dissipation:
- Ultra Compact Silicon Die Area:
Deliverables
- Datasheet
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog .v)
- Integration Guidelines and Support
- (Subject to Agreement)
Applications
- Connected Consumer Devices
- 802.11ac
- LTE
- DVB
- Home Network
- Wireline Communications
- Imaging
Block Diagram of the 12-bit 500MS/s Dual Channel IQ ADC
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