The S3ADS50M12BT40LPB is a compact and low power 12-bit SAR ADC IP.
This 12-bit ADC, sampling at 50MS/s, features an excellent performance including 75.0dB SFDR, 63.5dB SNR and 10.2-bit ENOB.
This high-end performance is obtained while dissipating ultra low power.
The S3ADS50M12BT40LPB can be cost-effectively ported across foundries and process nodes upon request.
- TSMC 40nm LP (Low-Power Process)
- 1.1V and 2.5V Supplies
- 12-bit SAR ADC
- 50MS/s Sampling Rate
- 8ns Analog Input Acquisition Time
- Internal Bandgap and Reference Buffer Included
- No External Accurate Reference required
- No External Reference Decoupling required
- Differential Input Signal Range: 1.0Vppdiff
- Outstanding Dynamic Performance:
- 75.0dB SFDR
- -75.0dB THD
- 63.5dB SNR
- 63.1dB SNDR
- 10.2-bit ENOB
- [Noise integrated up-to Nyquist]
- Power-Down and Idle Modes
- Low Power Dissipation
- Compact Die Area
- High Performance.
- Low Power.
- Small Area.
- Characterization Report
- Flat Netlist (cdl)
- Layout View (gds2)
- Abstract View (lef)
- Timing View (lib)
- Behavioural Model (Verilog)
- Integration Support
- Wireless Communications
- Wireline Communications
Block Diagram of the 12-bit 50MS/s ADC - TSMC 40nm LP