12-Bit 5MS/s DAC Programmable Voltage or Current Output
architecture with differential current outputs or voltage output
using internal load resistors. It uses 6 linear bits and 6 binary
bits, all of which are generated from within the current source
array.
This segmentation results in an excellent static performance
and reduced glitch energy at the output. This also ensures
parasitics within the DAC are minimized. Furthermore, the
distortion at the output is greatly reduced by using propriety
latch architecture.
The combination of static performance, reduced glitch energy,
minimized parasitics and reduced distortion, results in
outstanding dynamic performance over a wide range of
conditions including frequencies close to the DAC Nyquist
frequency.
This 12-bit DAC features an excellent static performance that
includes ±1LSB DNL and ±1.5LSB INL.
Dynamic performance highlights considering a signal frequency
with 1MHz and 5MHz conversion rate include an SNR of 68dB
and an SFDR of 70dBc.
The S3DA5M12BT40LPB is designed in a 40nm logic process,
which is ideal for integration with a DSP engine, and can be
cost-effectively ported across foundries and process nodes
upon request.
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Block Diagram of the 12-Bit 5MS/s DAC Programmable Voltage or Current Output
