Ridgetop’s rad-hard pipeline ADC is optimized for high performance applications that require very high input analog bandwidth and low power consumption, including spaceborne applications. This ADC is designed in the IBM 8HP silicon-germanium BICMOS process. The ADC has a full-speed, front-end sample-and-hold amplifier (SHA) that can accept input analog bandwidth to 1.5 GHz. The ADC structure shown in Figure 1 is a 2-channel time-interleaved pipeline ADC with an input SHA. The sampling frequency of the SHA can be as low as 650 MHz to under-sample the input IF-signal of 1.5 GHz. After the IF signal is sampled with the SHA, two channels of pipeline ADCs digitize the base-band signal. The sample rate of each channel is half of the sample rate of the SHA. Each pipeline channel consists of one 2.5-bit stage, eight 1.5-bit stages, and a 3-bit flash ADC at the end, which are available as building blocks for other ADCs. The sub-blocks include bandgap reference (BGR), three separate operational transconductance ampliers (OTAs), comparators, the ADC pipeline stages, and the SHA.