The 12-bit Dual Input ADC is a low-power 12-bit dual input ADC IP with a core sampling rate from 25MS/s up to 65MS/s.
The ADC employs a high-performance dual input sample-and-hold (S/H) circuit together with a differential pipeline architecture and digital error correction.
The dual input architecture enables this single ADC to be used as a complete IQ ADC solution. In this configuration, both S/H circuits are used and the single ADC core converts each channel alternately, thereby enabling very high channel-to-channel matching and minimum die area in IQ applications.
For maximum flexibility, the power dissipation of the ADC scales with the sampling frequency.
This 12-bit ADC features an excellent static performance that includes ±0.5LSB DNL and ±2.5LSB INL typ.
Dynamic performance highlights considering an input signal with 10MHz frequency, 65MS/s sampling rate for ADC core and 32.5MS/s sampling rate per channel, include SNR of 64dB, SFDR of 72dB and SNDR of 63dB, yielding 10.2ENOB performance.
Auxiliary circuits comprising a bandgap, frequency-dependent current biasing and internal reference buffers are also included.
The S3AD65MD12BT55 does not require any special analog options, and can be cost-effectively ported across foundries and process nodes upon request.
- 55nm 7 Metal TSMC CMOS LP Logic Process
- Single 1.2V Power Supply
- 12-Bit Pipeline ADC with Single Channel and IQ Operation
- Single Channel Operation: 25MS/s up to 65MS/s
- IQ Operation: 12.5MS/s up to 32.5MS/s per Channel
- Programmable Input Range
- DNL ±0.5LSB Typ.
- INL ±2.5LSB Typ.
- 64dB SNR Typ. @ fin= 10MHz
- 63dB SNDR Typ. (10.2ENOB) @ fin= 10MHz
- 72dB SFDR Typ. @ fin= 10MHz
- Low Power Dissipation
- Stand-by and Power Down Modes
- Compact Die Area
- Mobile Communications: HSPA, LTE
- WiFi, WiMax
- Powerline Communications
- DOCSIS, MoCA, DVB-C